A variety of electronic and optoelectronic devices can be enabled by developing thin film relaxed lattice constant III-V semiconductors on elemental silicon (Si) substrates. Surface layers capable of achieving the performance advantages of III-V materials may host a variety of high performance electronic devices such as complementary metal oxide semiconductor (CMOS) and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs).
Despite all these advantages, the growth of III-V materials upon silicon substrates presents many challenges. Crystal defects are generated by lattice mismatch, polar-on-nonpolar mismatch and thermal mismatch between the III-V semiconductor epitaxial layer and the silicon semiconductor substrate. When the lattice mismatch between the epitaxial layer and substrate exceeds a few percent, the strain induced by the mismatch becomes too great and defects are generated in the epitaxial layer when the epitaxial film relaxes the lattice mismatch strain. Many defects, such as threading dislocations and twins, tend to propagate into the “device layer” where the semiconductor device is fabricated.
In CMOS logic, high mobility n-metal oxide semiconductor (NMOS) and p-metal oxide semiconductor (PMOS) materials provide suitable characteristics for CMOS logic, which is predominately made using Si materials. However, low electron and hole mobility values using Si limit high speed and low power applications. Attempts have been made to obtain high performance NMOS using InSb III-V materials on polar substrate (e.g., GaAs) and PMOS using the high hole mobility germanium (Ge) material on nonpolar Si substrate. To date, integration of these two systems onto a single substrate platform has not been realized due to significant challenges.